Qinxin Yu email & phone information | Senior Asic Design Engineer, Engineering in Marvell Semiconductor (2012-10 - Now)

Qinxin Yu

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Senior Asic Design Engineer, Engineering in Marvell Semiconductor (2012-10 - Now)

Senior Memory Electrical Validation Engineer, Engineering in Intel Corporation (2017-04 - Now)

Validation Engineer, Engineering in Marvell Semiconductor (2014-07-01 - 2017-04)

Master Student in University Of Southern California (2012-08 - 2014-05)

Component Intern in Ge China Technology Center (2011-09 - 2012-01)

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China

Santa Clara, California, United States

Sunnyvale, California, United States

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n*********@h******.com + 3 more

linkedin + 4 more

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