Yi Cho email & phone information | Asic Design Verification Engineer, Engineering in Cisco

Yi Cho

View full profile

Unlock the full profile by signing up

Asic Design Verification Engineer, Engineering in Cisco

Senior Engineer, Engineering

Senior Design Verification Manager, Design in Marvell Semiconductor (2017-12 - 2018-04)

Staff Asic Design Verification Engineer, Engineering in Marvell Semiconductor (2015-09 - 2017-12)

Ì Ì in Stats Chippac (2016-06 - 2017-09)

+ 6 more

View all jobs

Taipei City, Taiwan, Taiwan

View all locations

y***@m******.com

linkedin + 3 more

View full profile

Increasing the level of data and fact checking when employing specialists in companies around the world.

Create account

Get a free trial right after registration. No card is required.

Create account